Current sources are one of the basic building blocks in Analog design. CMOS current mirror circuits are very accurate and simple compared to their Bipolar Junction Transistors (BJT) as MOS (Metal Oxide Semiconductor) input impedance is almost entirely capacitive. In ultra deep submicron technology (90/65 nm, technology), general assumption of the infinite DC input impedance of MOS is not entirely true, as the MOS in this domain has a dominant gate leakage current. The leakage current is amplified by a factor X which is the mismatch factor (or mirroring ratio of the current mirror circuit) of the transistors used in the circuit. Therefore it becomes difficult to mirror a small current with high accuracy and high mirroring ratio.
Further, output impedance of current source is an important parameter. The input and output headroom of a current source is generally important for determining the supply voltage or dynamic range of the current source. Cascoded current sources are usually preferred because of their low systematic offset due to their high output impedance. But these current sources often require higher input and output headroom. The input headroom is a sum of threshold voltage and overdrive voltage of a transistor used in the circuit.
There are active input current mirrors available but these current mirrors require a large input headroom. Further, in a simple current mirror that has a higher output conductance, gds, the drain to source voltage difference of the transistors may cause an error in the output current. This error is generally known as systematic offset. Cascoding the current mirror generally solves this problem by making the drain voltages same. However, cascading increases the input and output headroom requirements of the current mirror as mentioned earlier.
Furthermore, in ultra deep submicron technologies (e.g. 90 nm/65 nm process node), different types of transistors are available for selection. Therefore, mirror and cascode transistors may have to be carefully chosen to optimize area for better performance. In these circuits to reduce mismatch the mirror transistor may require a lower threshold voltage because the mismatch is lower for lower threshold voltages in case of submicron technology. The current mirroring error due to mismatch generally reduces linearly with overdrive voltage Von=VGS−VT, where VGS is the gate to source voltage and VT is the threshold voltage of the transistor. Therefore, the conventional biasing schemes may need higher headroom in highest overdrive corner, because bias margin on the mirror transistor is inversely proportional to the drive of the transistor.
Normally, in digital Complementary Metal Oxide Semiconductor (CMOS) processes the transistors are well controlled for VT and better drive current. This makes these transistors suitable for use as mirror transistor. For cascode, transistors with higher intrinsic gain (ratio of trans-conductance, gm, and output conductance, gds of a transistor) need to be selected. Therefore, thick gate oxide devices (or long channel devices) present in the process are generally good candidates for cascode, as they have small gds and moderate gm. Low voltage cascode using two different types of transistors can become difficult to bias across all PVT conditions in applications requiring low headroom.
Commonly used techniques for cascode biasing use transistors in linear region. This may require a higher headroom as the bias margin varies with PVT (process, voltage and temperature) and biasing different types of transistors as mirror and casecode transistor can become difficult with lower output headroom. In another possible biasing solution the transistors can be biased just on the edge of saturation by proper selection of transistors and current flowing through them. The margin for the mirror transistor can be adjusted using current flowing through the mirror. As a result, the bias margin of a transistor varies inversely with its drive. Therefore, it can require using large margins to bias the transistors across PVT. Although, the current mirror bias margin can remain constant across PVT for optimum headroom.